]> pilppa.com Git - linux-2.6-omap-h63xx.git/commitdiff
[TG3]: ethtool -d hangs PCIe systems
authorChris Elmquist <chrise@sgi.com>
Tue, 20 Dec 2005 21:25:19 +0000 (13:25 -0800)
committerDavid S. Miller <davem@sunset.davemloft.net>
Wed, 28 Dec 2005 21:04:52 +0000 (13:04 -0800)
Resubmitting after recommendation to use GET_REG32_1() instead of
GET_REG32_LOOP(..., 1).  Retested.  Problem remains fixed.

Prevent tg3_get_regs() from reading reserved and undocumented registers
at RX_CPU_BASE and TX_CPU_BASE offsets which caused hostile behavior
on PCIe platforms.

Acked-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/tg3.c
drivers/net/tg3.h

index cefb0c08a68d4999c2cb6cf6790f0349e75b9d2a..ce252c58b3e74893f04d0bba687d6905153e4d68 100644 (file)
@@ -7151,8 +7151,13 @@ do {     p = (u32 *)(orig_p + (reg));            \
        GET_REG32_LOOP(BUFMGR_MODE, 0x58);
        GET_REG32_LOOP(RDMAC_MODE, 0x08);
        GET_REG32_LOOP(WDMAC_MODE, 0x08);
-       GET_REG32_LOOP(RX_CPU_BASE, 0x280);
-       GET_REG32_LOOP(TX_CPU_BASE, 0x280);
+       GET_REG32_1(RX_CPU_MODE);
+       GET_REG32_1(RX_CPU_STATE);
+       GET_REG32_1(RX_CPU_PGMCTR);
+       GET_REG32_1(RX_CPU_HWBKPT);
+       GET_REG32_1(TX_CPU_MODE);
+       GET_REG32_1(TX_CPU_STATE);
+       GET_REG32_1(TX_CPU_PGMCTR);
        GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
        GET_REG32_LOOP(FTQ_RESET, 0x120);
        GET_REG32_LOOP(MSGINT_MODE, 0x0c);
index 94dbcf3537ec290e5b11e4481ce589fd673dcde5..890e1635996b56294fdaca69a9bb37e78ea7ce94 100644 (file)
 /* 0x280 --> 0x400 unused */
 
 #define RX_CPU_BASE                    0x00005000
+#define RX_CPU_MODE                    0x00005000
+#define RX_CPU_STATE                   0x00005004
+#define RX_CPU_PGMCTR                  0x0000501c
+#define RX_CPU_HWBKPT                  0x00005034
 #define TX_CPU_BASE                    0x00005400
+#define TX_CPU_MODE                    0x00005400
+#define TX_CPU_STATE                   0x00005404
+#define TX_CPU_PGMCTR                  0x0000541c
 
 /* Mailboxes */
 #define GRCMBOX_INTERRUPT_0            0x00005800 /* 64-bit */