[ARM] 4264/1: ldrex/strex syntax errors with recent compilers

Trying to build some code using atomic_clear_mask() on a ARM v6
processor with a recent compiler (tried with gcc version 4.1.1
(CodeSourcery ARM Sourcery G++ 2006q3-26), but
all gcc > 4.1 might be affected) results in the following:

/tmp/ccWKLJV8.s: Assembler messages:
/tmp/ccWKLJV8.s:581: Error: instruction does not accept this addressing
mode -- `ldrex r0,r3'
/tmp/ccWKLJV8.s:583: Error: instruction does not accept this addressing
mode -- `strex r1,r0,r3'

Older gcc (like gcc version 4.0.0 (DENX ELDK 4.1 4.0.0)) have no problem
with this.

The patch below fixes the compile error. I also verified that gcc-4.0.0 generates identical code using both forms.

Signed-off-by: Stelian Pop <stelian@popies.net>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/include/asm-arm/atomic.h b/include/asm-arm/atomic.h
index ea88aa6bfc78e91c9d0442ab2b504e3ddabe1c56..f266c2795124901fc05b6ba3cff0bb607e393655 100644 (file)
--- a/include/asm-arm/atomic.h
+++ b/include/asm-arm/atomic.h
@@ -103,9 +103,9 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
        unsigned long tmp, tmp2;
 
        __asm__ __volatile__("@ atomic_clear_mask\n"
-"1:    ldrex   %0, %2\n"
+"1:    ldrex   %0, [%2]\n"
 "      bic     %0, %0, %3\n"
-"      strex   %1, %0, %2\n"
+"      strex   %1, %0, [%2]\n"
 "      teq     %1, #0\n"
 "      bne     1b"
        : "=&r" (tmp), "=&r" (tmp2)