#if defined(CONFIG_USB_TUSB6010)
#define musb_ep_select(_mbase, _epnum) \
musb_writeb((_mbase), MUSB_INDEX, (_epnum))
-#define MGC_END_OFFSET MUSB_TUSB_OFFSET
+#define MUSB_EP_OFFSET MUSB_TUSB_OFFSET
/* "flat" mapping: each endpoint has its own i/o address */
#elif defined(MUSB_FLAT_REG)
#define musb_ep_select(_mbase, _epnum) (((void)(_mbase)),((void)(_epnum)))
-#define MGC_END_OFFSET MUSB_FLAT_OFFSET
+#define MUSB_EP_OFFSET MUSB_FLAT_OFFSET
/* "indexed" mapping: INDEX register controls register bank select */
#else
#define musb_ep_select(_mbase, _epnum) \
musb_writeb((_mbase), MUSB_INDEX, (_epnum))
-#define MGC_END_OFFSET MUSB_INDEXED_OFFSET
+#define MUSB_EP_OFFSET MUSB_INDEXED_OFFSET
#endif
/****************************** FUNCTIONS ********************************/
if (pImplChannel->transmit) {
csr = musb_readw(mbase,
- MGC_END_OFFSET(pImplChannel->epnum,MUSB_TXCSR));
+ MUSB_EP_OFFSET(pImplChannel->epnum,MUSB_TXCSR));
csr &= ~(MUSB_TXCSR_AUTOSET |
MUSB_TXCSR_DMAENAB |
MUSB_TXCSR_DMAMODE);
musb_writew(mbase,
- MGC_END_OFFSET(pImplChannel->epnum,MUSB_TXCSR),
+ MUSB_EP_OFFSET(pImplChannel->epnum,MUSB_TXCSR),
csr);
}
else {
csr = musb_readw(mbase,
- MGC_END_OFFSET(pImplChannel->epnum,MUSB_RXCSR));
+ MUSB_EP_OFFSET(pImplChannel->epnum,MUSB_RXCSR));
csr &= ~(MUSB_RXCSR_AUTOCLEAR |
MUSB_RXCSR_DMAENAB |
MUSB_RXCSR_DMAMODE);
musb_writew(mbase,
- MGC_END_OFFSET(pImplChannel->epnum,MUSB_RXCSR),
+ MUSB_EP_OFFSET(pImplChannel->epnum,MUSB_RXCSR),
csr);
}
musb_ep_select(mbase,
pImplChannel->epnum);
musb_writew(mbase,
- MGC_END_OFFSET(pImplChannel->epnum,MUSB_TXCSR),
+ MUSB_EP_OFFSET(pImplChannel->epnum,MUSB_TXCSR),
MUSB_TXCSR_TXPKTRDY);
} else
musb_dma_completion(
hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
#endif
- hw_ep->regs = MGC_END_OFFSET(i, 0) + mbase;
+ hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
#ifdef CONFIG_USB_MUSB_HDRC_HCD
hw_ep->target_regs = MUSB_BUSCTL_OFFSET(i, 0) + mbase;
hw_ep->rx_reinit = 1;