]> pilppa.com Git - linux-2.6-omap-h63xx.git/commit
[ARM] 4129/1: Add barriers after the TLB operations
authorCatalin Marinas <catalin.marinas@arm.com>
Mon, 5 Feb 2007 13:47:51 +0000 (14:47 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Thu, 8 Feb 2007 14:49:27 +0000 (14:49 +0000)
commite6a5d66f58431c66c79e236f722a5ad7dd959ef3
treef2153821e15aa4f5f30d02d0bc6d9a535ea168a4
parent9d99df4b10eef130dacb5f772cd589c625b03634
[ARM] 4129/1: Add barriers after the TLB operations

The architecture specification states that TLB operations are
guaranteed to be complete only after the execution of a DSB (Data
Synchronisation Barrier, former Data Write Barrier or Drain Write
Buffer). The branch target cache invalidation is also needed. The ISB
(Instruction Synchronisation Barrier, formerly Prefetch Flush) is
needed unless there will be a return from exception before the
corresponding mapping is used (i.e. user mappings).

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/mm/tlb-v6.S
include/asm-arm/tlbflush.h