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MIPS: TXx9: Cache fixup
authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>
Tue, 19 Aug 2008 13:55:09 +0000 (22:55 +0900)
committerRalf Baechle <ralf@linux-mips.org>
Sat, 11 Oct 2008 15:18:42 +0000 (16:18 +0100)
commitd10e025f0e4ba4b96d7b5786d232ac5b0b232b11
treea417a55071b4b7edc22b7c5bb1a2352e7b5986d9tree | snapshot
parent860e546c19d88c21819c7f0861c505debd2d6eedcommit | diff
MIPS: TXx9: Cache fixup

TX39/TX49 can enable/disable I/D cache at runtime.  Add kernel options
to control them.  This is useful to debug some cache-related issues,
such as aliasing or I/D coherency.  Also enable CWF bit for TX49 SoCs.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/txx9/generic/setup.c diff | blob | history
arch/mips/txx9/generic/setup_tx3927.c diff | blob | history
arch/mips/txx9/generic/setup_tx4927.c diff | blob | history
arch/mips/txx9/generic/setup_tx4938.c diff | blob | history
arch/mips/txx9/jmr3927/setup.c diff | blob | history
arch/mips/txx9/rbtx4927/setup.c diff | blob | history
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