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[ARM] Feroceon: small cleanups to L2 cache code
authorNicolas Pitre <nico@cam.org>
Thu, 11 Sep 2008 19:14:59 +0000 (15:14 -0400)
committerNicolas Pitre <nico@cam.org>
Tue, 30 Sep 2008 17:41:54 +0000 (13:41 -0400)
commit99c6bb390cf599b9e0aa6e69beacc4e5d875bf77
treed30e32867cd161001e5ae6fecc51a52f469bbafftree | snapshot
parent92a5de80e5c53c56d098ea3cb6266138efd892f6commit | diff
[ARM] Feroceon: small cleanups to L2 cache code

- Make sure that coprocessor instructions for range ops are contiguous
  and not reordered.

- s/invalidate_and_disable_dcache/flush_and_disable_dcache/

- Don't re-enable I/D caches if they were not enabled initially.

- Change some masks to shifts for better generated code.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Acked-by: Lennert Buytenhek <buytenh@marvell.com>
arch/arm/mm/cache-feroceon-l2.c diff | blob | history
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