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[ARM] 3267/1: PXA27x SSP controller register defines
authorDavid Vrabel <dvrabel@arcom.com>
Wed, 18 Jan 2006 22:38:44 +0000 (22:38 +0000)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Wed, 18 Jan 2006 22:38:44 +0000 (22:38 +0000)
commit68477d11769ce8c6830523f08637894c43885c7e
treea2e36829cc638c37e673a749306e31226d0ee2datree | snapshot
parent7eb9b2f56c9812d03ac63031869bcc42151067b1commit | diff
[ARM] 3267/1: PXA27x SSP controller register defines

Patch from David Vrabel

PXA27x SSP controller has a few different registers, including SCR (serial clock rate) in SSCR0.

Signed-off-by: David Vrabel <dvrabel@arcom.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
include/asm-arm/arch-pxa/pxa-regs.h diff | blob | history
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