OMAP3 clock: fix non-CORE DPLL rate assignment bugs

OMAP3 clock: fix non-CORE DPLL rate assignment bugs

Commit 8b1f0bd44fe490ec631230c8c040753a2bda8caa introduced a bug that
caused non-CORE DPLL rates to be incorrectly set on boot in
omap3_noncore_dpll_enable().  Debugged by Tomi Valkeinen
<tomi.valkeinen@nokia.com> - thanks Tomi.

Also fix omap3_noncore_dpll_set_rate() to assign clk->rate after a
DPLL reprogram.

Tested on 3430SDP.

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tomi Valkeinen <tomi.valkeinen@nokia.com>
Cc: Rick Bronson <rick@efn.org>
Cc: Timo Kokkonen <timo.t.kokkonen@nokia.com>
Cc: Sakari Poussa <sakari.poussa@nokia.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>