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ARM: OMAP: SoSSI: fix write / read cycle to tw1 mapping
authorImre Deak <imre.deak@solidboot.com>
Mon, 12 Jun 2006 15:17:33 +0000 (18:17 +0300)
committerJuha Yrjola <juha.yrjola@solidboot.com>
Mon, 12 Jun 2006 15:17:33 +0000 (18:17 +0300)
commit0976dc5e2d1501c31a2a33009617516b04b6da6a
tree7cc73c4fa3e9312f7a569d0c7b43ca3ffd0215f6tree | snapshot
parentf31800d88b2a42e055fc64505120a63113881474commit | diff
ARM: OMAP: SoSSI: fix write / read cycle to tw1 mapping

A read / write cycle is defined by tw0 + tw1. It was wrongly assumed that
the 1 cycle long CS active edge to read / write active edge is part of
each cycle, thus we ended up with too low tw1 value -> too short cycle
time.

Signed-off-by: Imre Deak <imre.deak@solidboot.com>
Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com>
drivers/video/omap/sossi.c diff | blob | history
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